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IoT, Embedded and Hardware Security

Hardware and Debug Interface Analysis

We examine the maintenance and debug interfaces on the device's circuit board. We assess whether someone with physical access could obtain data or control from the board.

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What it is

Interfaces such as JTAG, SWD and UART, used during manufacturing and testing, are often left open in the product. These interfaces may allow someone with access to read the firmware or gain control. The analysis examines whether they are closed after manufacturing. It also assesses whether data can be read from the memory chips.

Scope

  • Identifying maintenance and debug interfaces on the board, such as JTAG, SWD and UART
  • Testing whether these interfaces are closed after manufacturing
  • Assessing whether firmware and data can be read from the memory chips
  • Whether control can be gained through the bootloader
  • Examining the test points accessible once the casing is open

The need

When organizations need it

  • Before the final hardware revision is approved for mass production.
  • When your device will be used in an environment with physical access.
  • When your product is entering the EU market and you need to demonstrate that its attack surface is limited.

Method

How we work

  1. Board review

    We examine the circuit board and identify the maintenance and debug interfaces and memory chips.

  2. Access

    We assess in a controlled manner whether these interfaces are open and what they allow.

  3. Spread

    We determine whether the findings affect only one device or the entire model.

Outcome

What you have at the end

You gain a clear view of the device's physical access surface. Recommendations are provided to close open interfaces by hardware revision or configuration.

Frequently asked questions

Can this test damage the device?

Standard analysis does not harm the device. Steps that may cause damage, such as removing a memory chip from the board, are scoped separately and the number of devices is agreed in advance.

Is there a standard for debug interfaces?

ETSI EN 303 645 requires debug interfaces to be disabled or protected by access control. We conduct the review according to this standard.

IoT, Embedded and Hardware Security

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Let's talk about this service.

Tell us briefly what you need. We will agree on the scope and timing together in the first meeting.

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